Motorola 68000 · microcomputer.world

The 68000 presents eight 32-bit data registers and eight address-register names. Byte, word, and long operations share those registers; a 16-bit operation word selects their size and addressing modes. The active stack pointer is A7, backed by separate user and supervisor storage. Logical addresses retain 32 bits while the physical address bus exposes 24.

This specification is the sole maintained implementation and model contract for the original Motorola 68000. Its executable definitions generate the public class, stored state, views, instruction encodings and behavior, reset, execution, and exception/interrupt entry. Shared TypeScript services implement the declared mechanics. The language guide explains the notation; reference comparisons record independent cross-checks and their limits.

Historical setting

Introduced in 1979, the 68000 opened Motorola's 16/32-bit processor family. Its designers describe aiming beyond the 8-bit market toward systems previously built around minicomputers. Their oral history connects that ambition to the earlier 6800 business and the decision to invest in a new architecture. It later powered the original Macintosh; the specification models the processor, while a Macintosh needs its own memory map and devices. See the Macintosh processor history.

The physical processor and this model

The 68000 combines 32-bit registers with a 16-bit external data bus and a 16 MiB byte-address space. Address pins A23–A1 identify a word; upper/lower data strobes select its byte lanes. Even-addressed bytes occupy the upper lane. A long therefore requires more than one bus transfer. In an asynchronous bus cycle, the selected memory or peripheral acknowledges completion with DTACK; external logic can report failure with BERR. Function-code outputs distinguish access spaces. Motorola's user's manual, chapters 2, 3, and 5 explains these signals and transfers.

Here the connection transfers individual bytes and records successful calls. The model preserves logical addresses, byte order, and declared commit points, but does not simulate clock edges, strobes, wait states, bus arbitration, or prefetch. In particular, a modeled bus error can occur between the two bytes of a hardware word transfer. Fault recovery below describes this abstraction, not a promise of identical partial execution on silicon. Later 680x0 extensions, caches, and virtual-memory machinery are outside this original-chip model.

Stored state

D0–D7 and A0–A6 are independent 32-bit registers. USP and SSP store the two stack pointers; there is no additional stored A7. PC retains its full logical address, IR the current operation word, and the interrupt mask three bits. The entry group records exception-frame bookkeeping, separate from architectural flags. HALTED, FAULTED, and TRACEPENDING support the execution boundary.

cpu "68000" boundary word
state {
  register D0: 32
  register D1: 32
  register D2: 32
  register D3: 32
  register D4: 32
  register D5: 32
  register D6: 32
  register D7: 32
  register A0: 32
  register A1: 32
  register A2: 32
  register A3: 32
  register A4: 32
  register A5: 32
  register A6: 32
  register USP: 32
  register SSP: 32
  register PC: 32
  register IR: 16
  register INTERRUPTMASK: 3 = interruptMask
  latch HALTED
  latch FAULTED
  latch TRACEPENDING = tracePending
  group ENTRY {
    choice KIND: "none", "reset", "fault", "exception", "trap"
    register VECTOR: 8
  }
  flag X
  flag N
  flag Z
  flag V
  flag C
  flag T
  flag S
}

Construction and inspection

new Cpu68000(memory, initialState, connections?) requires a 16 MiB address space and all these stored fields:

Fields	Constraint
`d0`–`d7`	Unsigned 32-bit data registers
`a0`–`a6`	Unsigned 32-bit address registers
`usp`, `ssp`	Unsigned 32-bit user and supervisor stack pointers
`pc`	Unsigned 32-bit program counter
`ir`	Unsigned 16-bit last completely fetched operation word
`interruptMask`	Integer from 0 through 7
`halted`	Boolean STOP latch; required in initial state
`faulted`	Boolean terminal double-fault latch; only external reset releases it
`tracePending`	Boolean owed-trace latch; required independently of T and STOP
`entry.kind`	`none`, `reset`, `fault`, `exception`, or `trap`: phase awaiting its first opcode fetch
`entry.vector`	Unsigned byte identifying that exception vector; ignored for `none` and `reset`
`flags.x/n/z/v/c`	Boolean extend, negative, zero, overflow, and carry
`flags.t/s`	Boolean trace and supervisor bits

The original status register has X/N/Z/V/C at bits 4–0, interrupt mask at 10–8, S at 13, and T at 15. There is no master-mode bit or second trace bit. Instructions pack and unpack SR/CCR from these fields; snapshots keep no duplicate packed register. STOP sets halted; completed instructions that began with T set owe a trace through tracePending. All three latches are stored in snapshots. faulted takes priority over STOP, trace, and interrupt recognition. ir changes as soon as both opcode bytes have been read; extension fetches, trace, and interrupt entry preserve it. An odd instruction PC therefore stacks the supplied or previously fetched IR. Synchronous exceptions and trace ignore the interrupt mask; external requests use the level rules below. Entry clears T and selects SSP.

The exported cpu68000StateDescription is generated from the state block above. It supplies field names and constraints to construction and machine parsing. Construction reads each declared field once, validates it, and owns a copy. Numeric and named-choice errors throw RangeError; missing or invalid flag groups and Boolean fields throw TypeError. Extra metadata and derived views are ignored. Construction does not read RAM, reset, or execute.

snapshot() owns a detached copy with readonly TypeScript types. It adds:

a7: ssp when S is set, otherwise usp. The active pointer is a view, so switching modes cannot leave a duplicate A7 value out of sync.
physicalPc: the low 24 bits of pc.

Snapshots can initialize another CPU. Neither inspection nor snapshot copying accesses RAM. Mutating caller state or an earlier snapshot cannot alter the CPU.

entry preserves the context of the next initial opcode fetch across snapshots. Ordinary initial state uses { kind: "none", vector: 0 }. Successful reset sets reset; bus/address-error entry sets fault; group-1 exceptions, trace, and interrupts set exception; group-2 instruction traps set trap. The vector distinguishes, for example, TRAP #0 from TRAP #1. A complete opcode fetch clears the context to none, vector 0; a partial fetch preserves it. This records entry sequencing without storing a prefetch queue. The existing trace/interrupt boundary priority still applies before that fetch.

Memory connection

MemoryConnection describes size, read(address), and write(address, value). Addresses reaching it are physical 24-bit addresses. A successful read returns an integer byte; a successful write returns nothing. Either operation can return "bus-error" to report a failed transfer. The connection must report failure without completing that byte, including any device side effect. size describes the address space, so unmapped regions need not allocate RAM.

For example, a machine can expose a small RAM region on the full address bus:

const memory: MemoryConnection = {
  size: 0x1000000,
  read: address => address < ram.size ? ram.read(address) : "bus-error",
  write: (address, value) => address < ram.size ? ram.write(address, value) : "bus-error",
};

Only this explicit result signals an emulated bus error. Thrown host values, even the string "bus-error", propagate unchanged. Invalid successful read values throw RangeError; a write returning another value throws TypeError. The shared recorder logs a byte only after its transfer succeeds. The failed byte appears in fault metadata, while earlier successful bytes remain in order.

Logical and physical addresses

Registers retain all 32 bits, including PC and both stack pointers. Sequential instruction fetching advances PC modulo 2³². RAM access uses the low 24 bits of an address, matching the original processor's physical address space. For example, PC AB001000 reads its first byte at physical 001000.

Words and long words are big-endian. A long word contains its most significant word first, and each word contains its most significant byte first. Data accesses continue across the physical FFFFFF boundary at 000000. Instruction words, word operands, and long operands require even addresses. A long word at an address ending in 2 is valid. Byte accesses have no alignment restriction.

The shared runner compares snapshot().pc, retaining all 32 bits. Accordingly, a machine file's end uses the full PC while its memory blocks use physical addresses. Machine images must fit RAM; loading an image never wraps.

A7 and physical addresses

S selects the stack bank at each operand's turn: clear means USP, set means SSP. Reading A7 reads only that selected register. Capturing the choice separately lets an exchange resolve both register identities before reading either value, and retain those identities through writeback. The bank view returns zero for user storage and one for supervisor storage.

view STACKBANK "active stack bank" : 8 {
  supervisor = flag S
  return select(supervisor, u8(1), u8(0))
}
view A7 "active stack pointer" : 32 {
  bank = source STACKBANK
  pointer = choose not(zero(bank)) : 32 {
    then {
      stack = register SSP
      return stack
    }
    else {
      stack = register USP
      return stack
    }
  }
  return pointer
}
view PHYSICALPC "physical program address" : 32 {
  logical = register PC
  return and(logical, u32($FFFFFF))
}

The three-bit address code names A0–A7. Selecting A7 captures its current bank; internal codes seven and eight then identify USP and SSP respectively. This selection reads S only for A7 and does not read either stack pointer yet.

codes addressRegisters {
  000 "A0"
  001 "A1"
  010 "A2"
  011 "A3"
  100 "A4"
  101 "A5"
  110 "A6"
  111 "A7"
}
source selectAddressRegister "select address-register storage" (code: 3) : 8 {
  selected = choose equal(code, u3(7)) : 8 {
    then {
      bank = source STACKBANK
      return add(u8(7), bank)
    }
    else {
      return extend(code, 8)
    }
  }
  return selected
}
operands addressStorage {
  000 "A0" = register A0
  001 "A1" = register A1
  010 "A2" = register A2
  011 "A3" = register A3
  100 "A4" = register A4
  101 "A5" = register A5
  110 "A6" = register A6
  111 "USP" = register USP
}
source readAddressRegister "read selected address register" (selected: 8) : 32 {
  contents = match selected : 32 {
    case "00000rrr" for r in addressStorage {
      original = operand r
      return original
    }
    case "00001000" {
      original = register SSP
      return original
    }
    otherwise unsupported
  }
  return contents
}
action writeAddressRegister "write selected address register" (selected: 8, contents: 32) {
  match selected {
    case "00000rrr" for r in addressStorage {
      operand r <- contents
    }
    case "00001000" {
      SSP <- contents
    }
    otherwise unsupported
  }
}

Condition codes and status

CCR packs X, N, Z, V, C into bits 4 through 0. SR additionally holds T in bit 15, S in bit 13, and the interrupt mask in bits 10–8; reserved bits read as zero. Capture SR in the established order: T, S, interrupt mask, then X/N/Z/V/C. CCR writes update those five flags in place. Full SR writes then update T/S and finally the interrupt mask, preserving the existing flag object.

view CCR "condition code register" : 16 {
  x = flag X
  n = flag N
  z = flag Z
  v = flag V
  c = flag C
  return extend(pack<8>(0, 0, 0, x, n, z, v, c), 16)
}
view SR "status register" : 16 {
  trace = flag T
  supervisor = flag S
  mask = register INTERRUPTMASK
  condition = source CCR
  high = pack<8>(trace, 0, supervisor, 0, 0, bit(mask, 2), bit(mask, 1), bit(mask, 0))
  return concat(high, lowByte(condition))
}
policy conditionCode "restore condition codes" (contents: 16) {
  X = bit(contents, 4)
  N = bit(contents, 3)
  Z = bit(contents, 2)
  V = bit(contents, 1)
  C = bit(contents, 0)
}
policy systemFlags "restore system flags" (contents: 16) {
  T = bit(contents, 15)
  S = bit(contents, 13)
}
action writeCCR "write condition code register" (contents: 16) {
  apply conditionCode(contents)
}
action writeSR "write status register" (contents: 16) {
  perform writeCCR(contents)
  apply systemFlags(contents)
  INTERRUPTMASK <- bits(contents, 10, 8)
}

Data-register results

A byte or word write preserves the live upper part of its data register. The three result policies set N from the size's sign bit, set Z for zero, and clear V/C. They preserve X/T/S and serve the specification’s arithmetic families.

operands dataRegisters {
  000 "D0" = register D0
  001 "D1" = register D1
  010 "D2" = register D2
  011 "D3" = register D3
  100 "D4" = register D4
  101 "D5" = register D5
  110 "D6" = register D6
  111 "D7" = register D7
}
policy resultFlags<bits: 8, 16, 32> "68000 result" (result: bits) {
  N = negative(result)
  Z = zero(result)
  V = 0
  C = 0
}

Register transfers

MOVE uses 00 zz ddd mmm sss rrr: zz=01 is byte, 10 long, 11 word. The destination occupies ddd/mmm; the source sss/rrr. Mode 000 names Dn, mode 001 An. Byte forms exclude address registers. Destination mode 001 selects MOVEA, which sign-extends a word and preserves every flag.